1. Field
Various features relate to a substrate that includes inorganic material that lowers the coefficient of thermal expansion (CTE) and reduces warpage.
2. Background
A substrate is typically made of a central core layer and multiple dielectric layers on either side of the central core layer. Copper or other conductive material is used on the surface of the core and dielectric layers to route signals from the active component of an integrated circuit (IC)/die to the motherboard and other components in a device. The core layer includes a cured dielectric layer with metal (e.g., copper) foil bonded on both sides of the cured dielectric layer (e.g., resin). The buildup dielectric layer is often referred to as a prepreg (pre-impregnated) layer or buildup epoxy and may be laminated or pressed on top of the core during manufacturing.
FIG. 1 illustrates a die that is coupled (e.g., mounted) on a conventional substrate. Specifically, FIG. 1 illustrates a substrate 100 on which a die 102 is mounted. The substrate 100 is a package substrate. As shown in FIG. 1, the substrate 100 includes a core layer 104, a first dielectric layer 106, a first solder resist layer 110, a second solder resist layer 112, a first set of traces 114, a second set of traces 116, a first set of pads 120, a second set of pads 122, a first via 124, a second via 126, and a third via 128.
The substrate 100 also includes a first set of solder balls 130 and a second set of solder balls 132. The die 102 is coupled (e.g., mounted) to the substrate 100 through the first set of solder balls 130. The second set of solder balls 132 is configured to be coupled to a printed circuit board (PCB).
One major issue and concern that manufacturers of substrates face is the warpage of the substrate during IC/die/chip and/or board mount, which can lead to surface mount yield issues. These high temperature warpage problems are related to material properties including the coefficient of thermal expansion (CTE) of the materials comprising the substrate. In essence, the IC/die (that is mounted on a substrate) is made of material that typically has a CTE that is substantially different than the CTE of the substrate. Typically, the substrate has a CTE that is greater than the CTE of the IC/die. This is because the substrate includes more metal material than the IC/die. The metal material (e.g., copper) has a CTE that is much greater than the material of the IC/die. The difference in the CTEs of the IC and the substrate is was causes the warpage issue during the IC/die mounting on the substrate, as the IC will expand and contract differently than the substrate. In FIG. 1 the core layer 104 has a CTE that is different than the CTE of the die 102. This difference in CTE may cause warpage issue and thus result in a defective die package.
Therefore there is need for a substrate that has a CTE that is closer to the CTE of the IC/die, in order to reduce warpage issues during the mounting of the IC/die on the substrate and thus increasing the surface mount yield of dies that are mounted on a substrate.